Digital electronic systems are often operated with multiple power domains. For example, a central processing unit (CPU) may have different power domains for its core, its input/output (I/O), and its various memories (e.g. DRAM, Flash), etc. Also, due to resistive and reactive elements found in, for example, integrated circuits (ICs) and the printed circuit boards (PCBs) on which these ICs are mounted, power domains that are nominally at the same voltage level may “bounce” in such a fashion that, for a transient period, they are operating at different voltage levels. If digital signals are being transmitted from one power domain to another, voltage transients or “bounce” can cause data errors. For example, in a system where two voltage domains are nominally at 2 volts (V) each, if a “noisy” domain has a bounce of 1V, data transmitted from a “quiet” domain to the noisy domain can be corrupted. As used herein, “noisy” refers to a power domain with appreciable power and/or ground rail bounce, and “quiet” refers to a power domain which the ground and power rail potentials are relatively stable. It is recognized that in typical applications, most power rails have non-zero noise.
In switching power converter IC design, a significant concern is how to transfer signal between a quiet ground domain and a noisy power ground domain. The power ground domain is typically noisy because, to achieve high power efficiency, power devices are required to switch very fast to reduce switching commutation loss. Fast di/dt changes across parasitic inductances in power ground paths can lead to large magnitude power ground (PG) ringing. In mobile core buck applications, the PG ringing can be more than +/−1V, with spectral content up to several hundred MegaHertz. In VRM/datacenter applications, PG ringing has been reported to be 1-3V. Many logic families cannot communicate reliably between power domains which differ by such large magnitudes.
A typical logic family has a noise margin, defined as the difference between the worst case output of the driving logic gate and the worst case input of the receiving logic gate, in the range of 10-20% of the logic rail voltage. With certain logic families, the noise margin may be as high at 50% of the logic rail (“logic”) voltage. For example, 1.8V CMOS has a logic noise margin of around 200 mV. Power rail noise subtracts from this logic family noise margin, and when sufficiently large, can cause logic communication errors. Level shift logic elements have been used between domains to mitigate these errors.
As will be appreciated by those of ordinary skill in the art, Logic Noise Margin (LNM) is the difference between what the driver IC outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic voltage. There are two different types of noise margin, one for a logic high value [1] and one for a logic low value [0]. For a valid logic high, the worst case noise margin for the circuit is the minimum high level voltage which may be output from the driver; minus, the minimum high level voltage which may be seen at the receiver IC. For a valid logic low, the worst case noise margin for the circuit is the maximum low level voltage which may be output from the driver; minus, the maximum low level voltage which may be seen at the receiver IC.
With such large magnitude PG ringing noise, it can be challenging to design level shifters to transfer signals between the power domains, especially if the noise magnitudes are comparable to the voltage ratings of the available level shift transistors. In prior art designs, high voltage devices were used to handle large PG ringing, to avoid device voltage rating issues or to pass the electrical rules checker.
Prior art logic level shifters use high voltage devices to absorb the voltage differences between low voltage logic rails. For example, in FIG. 1, a logic level shifter 10 includes high voltage devices MN1, MN2, MP1, MP2, MP3, and MP4 to absorb voltage differences between the low voltage logic rails VDD and PV due to voltage differences between the PV/PG domain and the VDD/VSS domain. As an example, if VSS and PG are nominally at ground, and if VDD and PV are nominally at 2V, PV might reach, for example, 3V due to a bounce of 1V in PG. Therefore, while an inverter 12 can be made with 2V transistors, the transistors MN1, MN2, and MP1-MP4 must be made with at least 3V transistors, and more likely 5V transistors. This is disadvantageous in that using devices with higher voltage ratings compared to the standard logic gates 1) adds propagation delay; 2) limits low supply voltage operation; 3) increases process cost by requiring higher voltage devices; 4) increases product cost due to larger area of higher voltage devices; and/or 5) requires large/complex cascode circuitry to achieve high voltage operation using only low voltage devices.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.